The present invention relates to a bipolar transistor and a Bi-CMOS device including the bipolar transistor, and also relates to a manufacturing method for the bipolar transistor and the Bi-CMOS device.
There have been demanded large scale and high performance of LSIs. In particular, Bi-CMOS devices are remarkable since they have the advantage of CMOS transistors such as high integration and low power consumption and the advantage of bipolar transistors such as high-speed operation.
Such Bi-CMOS devices have a composite element structure of CMOS transistors and bipolar transistors. In general, a manufacturing method for a Bi-CMOS device is complex with many steps to cause a high manufacturing cost.
FIG. 1 is a sectional view of a bipolar transistor to be formed in a manufacturing process for a CMOS transistor in a Bi-CMOS device in the prior art.
Referring to FIG. 1, reference numeral 1 designates a semiconductor substrate such as a p-type monocrystal silicon substrate, and reference numeral 2 designates a semiconductor layer formed at an upper portion of the semiconductor substrate. The semiconductor layer 2 is formed as an n.sup.+ epitaxial growth layer.
An n.sup.+ collector buried region 3 is formed in the semiconductor layer 2 and the semiconductor substrate 1.
A p-type base region 4 is formed at an upper portion of the semiconductor layer 2 above the n.sup.+ collector buried region 3. An n.sup.+ emitter region 5 is formed at an upper portion of the p-type base region 4. A p.sup.+ graft base region 6 is formed at the upper portion of the semiconductor layer 2 so as to connect with a periphery of the p-type base region 4.
An element isolating region 7 is formed in the semiconductor layer 2, and an n.sup.+ collector drawn region 8 is formed in the semiconductor layer 2 so as to connect with the n.sup.+ collector buried region 3 and be arranged on the side of the p-type base region 4 adjacent to the element isolating region 7.
A base electrode 9, emitter electrode 10 and collector electrode 11 are formed on the p.sup.+ graft base region 8, the n.sup.+ emitter region 5 and the n.sup.+ collector drawn region 8 of the semiconductor layer 2, respectively.
An offset insulating film 12 is formed on the p-type base region 4 around the n.sup.+ emitter region 5. An emitter side wall insulating film 13 is formed on a side wall of the emitter electrode 10 so as to connect with the offset insulating film 12.
A manufacturing method for the NPN bipolar transistor shown in FIG. 1 will now be described with reference to FIGS. 2A to 2C.
In the first step shown in FIG. 2A, an n.sup.+ collector buried region 3 is formed in an upper layer of a semiconductor substrate 1 such as a p-type monocrystal silicon substrate by an ion implantation process. Then, a semiconductor layer 2 such as an n-type epitaxial growth layer is formed on an upper surface of the semiconductor substrate 1 by an epitaxial growth process.
Then, a plurality of element isolating regions 7, 14 and 15 are formed at an upper portion of the semiconductor layer 2 by a LOCOS process.
Then, upper surfaces of the element isolating regions 7, 14 and 15 and the semiconductor layer 2 are flattened by an etch-back process.
Then, a first insulating film 16 is formed on the upper surface of the semiconductor layer 2 by a thermal oxidation process.
Then, a first polysilicon film 17 is formed on the entire upper surface of the semiconductor layer 2 so as to cover the first insulating film 16 and the element isolating regions 7, 14 and 15 by a CVD (Chemical Vapor Deposition) process.
Then, a portion (shown by a two-dot chain line) of the first polysilicon film 17 is removed by a photolithography and etching process to form a mask pattern 18 as the remaining portion of the first polysilicon film 17.
Then, a portion (shown by a one-dot chain line) of the first insulating film 16 is removed by an RIE (Reactive Ion Etching) process using the mask pattern 18 as an etching mask, thereby forming an offset insulating film 12 as the remaining portion of the first insulating film 16 on a base forming region 20 around an emitter forming region 19.
In the second step shown in FIG. 2B, a second polysilicon film 21 is formed on the entire upper surface of the semiconductor layer 2 so as to cover the mask pattern 18 by a CVD process. Then, a portion (shown by a one-dot chain line) of the second polysilicon film 21 and a portion (shown by a dashed line) of the mask pattern 18 are removed by a photolithography and RIE process to form a base electrode 9, an emitter electrode 10 and a collector electrode 11 as the remaining portion of the second polysilicon film 21.
Then, an n.sup.+ collector drawn region 8 is formed at the upper portion of the semiconductor layer 2 between the element isolating regions 7 and 15 so as to connect with the n.sup.+ collector buried region 3 by an ion implantation process.
In the third step shown in FIG. 2C, a second insulating film 22 such as a silicon oxide film is formed on the entire upper surface of the semiconductor layer 2 so as to cover the electrodes 8, 10 and 11 by a CVD process.
Then, a portion (shown by a two-dot chain line) of the second insulating film 22 is removed by an etch-back process to form an emitter side wall insulating film 13 on a side wall of the emitter electrode 10.
Then, boron ions are implanted into the upper portion of the semiconductor layer 2 by an ion implantation process to form a p.sup.+ graft base region 6 on the opposite sides of the base forming region 20.
Then, boron ions are implanted into the emitter electrode 10 by an ion implantation process, and then the boron ions in the emitter electrode 10 are diffused into the base forming region 20 by an impurity diffusion process to form a p-type base region 4 connected with the p.sup.+ graft base region 6.
Then, arsenic ions are implanted into the emitter electrode 10 by an ion implantation process, and then the arsenic ions in the emitter electrode 10 are diffused into an upper portion of the p-type base region 4 by an impurity diffusion process to form an n.sup.+ emitter region 5.
In this manner, the NPN bipolar transistor shown in FIG. 1 is manufactured.
In the prior art bipolar transistor mentioned above, however, a distance between the base electrode 9 and the emitter electrode 10 is decided by a resolution in the photolithography process. Accordingly, in order to obtain a sufficient resolution in the photolithography process, a sufficient distance W between the emitter electrode 10 and a base contact portion 24 must be defined. Even in the case of a photolithography process using an excimer laser, the distance W becomes about 0.25-0.3 .mu.m.
Accordingly, the bipolar transistor cannot be sufficiently reduced in size. As a result, a collector--base parasitic capacitance and a collector saturation parasitic capacitance cannot be reduced to cause a reduction of a cut-off frequency and an elongation of a delay time. Accordingly, electrical characteristics of the bipolar transistor is reduced.
FIG. 3 shows an example of a Bi-CMOS device in the prior art.
Referring to FIG. 3, the Bi-CMOS device includes a p-type semiconductor substrate 31, n.sup.+ buried layer 32, n-type epitaxial growth layer 33, p-type well 34p of an n-type MOS transistor, n-type well 34n of a p-type MOS transistor, p-type isolation layer 34pi, selective oxide film 35, gate insulating film 36, gate electrodes 37 formed of polysilicon, n.sup.+ collector drawn region 38, LDD 39 of the n-type MOS transistor, gate side wall insulating film 40 formed on a side wall of each gate electrode 37, source and drain 41 of the n-type MOS transistor, emitter window opening insulating film 42, p.sup.+ base drawn region 43 selectively formed in a base region 27 formed in the n-type epitaxial growth layer 33, source and drain 44 of the p-type MOS transistor, emitter window 45 formed through the emitter window opening insulating film 42, emitter polysilicon layer 46, n.sup.+ collector electrode drawn portion 37, emitter region 48 formed by diffusing an impurity in the emitter polysilicon layer 46 to a surface portion of the base region 27, interlayer insulating film 49, contact holes 50 and 50e formed through the interlayer insulating film 49, and aluminum electrodes 26.
The Bi-CMOS device mentioned above is manufactured by forming the n.sup.+ buried region 32 at a surface portion of the p-type semiconductor substrate 31, forming the n-type epitaxial growth layer 33, forming the n-type well 34n, the p-type well 34p and the p-type isolation layer 34pi, forming the gate insulating film 36, the gate electrodes 37, the n.sup.+ collector drawn region 38, the base region 27, the LDD 39, the source and drain 44 of the n-type MOS transistor and the source and drain 41 of the p-type MOS transistor, forming the p.sup.+ base drawn region 43, entirely forming the emitter window opening insulating film 42, etching the insulating film 42 to form the emitter window 45, forming the emitter polysilicon layer 46 and patterning the same, forming the emitter region 48 by diffusion, forming the interlayer insulating film 49, forming the contact holes 50 and 50e, and forming the electrodes 26 after flattening the upper surface by reflowing.
However, the prior art Bi-CMOS device shown in FIG. 3 has the following problems.
First, an etching depth at a portion of the interlayer insulating film 49 where the emitter contact hole 50e is to be formed is different by a thickness of the emitter window opening insulating film 42 from an etching depth at another portion of the interlayer insulating film 49 where the other contact holes 50 are to be formed. Accordingly, the emitter polysilicon layer 46 is overetched to be thinned by anisotropic etching for the formation of the contact holes 50e and 50. As a result, there is a possibility that the aluminum electrode 26 to be later formed in the emitter contact hole 50e will penetrate through the emitter polysilicon layer 46, or a variation in characteristics will occur. However, if the emitter polysilicon layer 46 is not overetched, the contact holes 50 other than the emitter contact hole 50e will not be perfectly formed, so that the upper surface of the semiconductor substrate 31 cannot be exposed.
Secondly, there is a possibility that the upper surface of the base region 27 is damaged by anisotropic etching for the formation of the gate side wall insulating film 40 which is essential to obtain a MOS transistor having an LDD structure, causing an increase in leakage current in the bipolar transistor.
That is, in the stage where the gate side wall insulating film 40 is to be formed, the base region 27 of the bipolar transistor is covered with only the gate insulating film 36 formed before the formation of the gate electrodes 37. Accordingly, it cannot be avoided that the upper surface of the base region 27 is damaged by the overetching by RIE. Such damage of the upper surface of the base region 27 causes an increase in leakage current in the bipolar transistor.
Thirdly, as previously mentioned, the thicker the emitter window opening insulating film 42, the more the emitter polysilicon layer 46 must be overetched. Therefore, it is obliged to reduce the thickness of the insulating film 42. However, the reduction in the thickness of the insulating film 42 causes an increase in emitter--base parasitic capacitance to reduce a high-speed operability. That is, the emitter polysilicon layer 46 is so patterned as to fully cover the emitter window 45 and extend laterally. Such an extended portion of the emitter polysilicon layer 46 is opposed to the upper surface of the base region 27 with the emitter window opening insulating film 42 interposed therebetween. As a result, an electrostatic capacitance is generated between the extended portion and the base region 27, causing the increase in the emitter--base parasitic capacitance.
Accordingly, it is necessary to reduce the parasitic capacitance. This is effectively attained by thickening the emitter window opening insulating film 42, but the thickening of the insulating film 42 is not permitted for the above reason.
Finally, the formation of the base drawn region 43 by the ion implantation must precede the formation of the emitter region 48 by the thermal diffusion. Accordingly, it is difficult to shallow the base drawn region.
That is, if the base drawn region 43 is formed after the formation of the emitter region 48, the ion implantation for the formation of the base drawn region 43 must be performed through the emitter window opening insulating film 42, with the result that a high dose of ions to be implanted cannot be obtained. For this reason, the ion implantation for the formation of the base drawn region 43 must precede the formation of the emitter region 48.
However, since the base drawn region 43 is formed before the formation of the emitter region 48, the base drawn region 43 previously formed is diffused to be expanded by the heating in forming the emitter region 48. This causes an increase in collector--base parasitic capacitance and hinders high integration of elements.
FIG. 4 shows an example of a very high speed Bi-CMOS device in the prior art.
Referring to FIG. 4, a semiconductor layer 52 such as an n-type epitaxial growth layer is formed at an upper portion of a semiconductor substrate 51. The semiconductor layer 52 includes a plurality of element isolating regions 53, a bipolar transistor forming region 54, an n-type MOS transistor forming region 55 of a CMOS transistor, and a p-type MOS transistor forming region 56 of the CMOS transistor. The bipolar transistor forming region 54, the n-type MOS transistor forming region 55 and the p-type MOS transistor forming region 56 are isolated from each other by the element isolating regions 53.
An NPN bipolar transistor 61 is formed in the bipolar transistor forming region 54. The NPN bipolar transistor 61 has the following structure. That is, an n.sup.+ collector buried region 62 is formed at an upper portion of the semiconductor substrate 51 and a lower portion of the semiconductor layer 52. A p-type base region 63 is formed at the upper portion of the semiconductor layer 52 above the n+collector buried region 62. An n.sup.+ emitter region 64 is formed at an upper portion of the p-type base region 63. A p.sup.+ graft base region 65 is formed at the upper portion of the semiconductor layer 52 on one side of the p-type base region 63. An n.sup.+ collector drawn region 66 connected with the n.sup.+ collector buried region 62 is formed in the semiconductor layer 52 on the other side of the p-type base region 63 so as not to be connected with the p-type base region 63.
A base electrode 67, an emitter electrode 68 and a collector electrode 69 all formed from the same polysilicon film is formed on the semiconductor layer 52 so as to be connected with the p.sup.+ graft base region 65, the n.sup.+ emitter region 64 and the n.sup.+ collector drawn region 66, respectively.
Further, a first interelectrode insulating film 70A is formed between the base electrode 67 and the emitter electrode 68, and a second interelectrode insulating film 70B is formed between the emitter electrode 68 and the collector electrode 69.
On the other hand, an n-type MOS transistor 71 Is formed In the n-type MOS transistor forming region 55, and a p-type MOS transistor 81 IIs formed in the p-type MOS transistor forming region 56. Gates 71 and 82 are formed on the n-type MOS transistor 71 and the p-type MOS transistor 81 through gate insulating films 92, respectively. The gates 71 and 82 are formed from the polysilicon film forming the electrodes 67, 68 and 69 of the NPN bipolar transistor 61. A source and drain region 73 having an LDD structure is formed at the upper portion of the semiconductor layer 52 on the opposite sides of the gate 72. Similarly, a source and drain region 83 having an LDD structure is formed at the upper portion of the semiconductor layer 52 on the opposite sides of the gate 82.
The very high speed Bi-CMOS device shown in FIG. 4 is manufactured in the following manner.
In the first step, an n.sup.+ collector buried region 62 is formed at an upper portion of a semiconductor substrate 51 such as a p-type monocrystal silicon substrate by an ordinary method. Then, a semiconductor layer 52 such as an n-type epitaxial growth layer is formed on an upper surface of the semiconductor substrate 51 by an epitaxial growth process.
Then, a plurality of element isolating regions 53 are formed at an upper portion of the semiconductor layer 52 by a LOCOS process. Then, upper surfaces of the element isolating regions 53 are flattened by an etch-back process.
Then, a first insulating film is formed on an upper surface of the semiconductor layer 52 by a thermal oxidation process.
Then, a portion of the first insulating film in a bipolar transistor forming region 54 is removed by a photolithography and etching process to form gate insulating films 92 in an n-type MOS transistor forming region 55 and a p-type MOS transistor forming region 56.
In the second step, a polysilicon film is formed on the entire upper surface of the semiconductor layer 52 so as to cover the gate insulating films 92 by a CVD process.
In the third step, a predetermined portion of the polysilicon film is removed by a photolithography and etching process to form a base electrode 67, an emitter electrode 68 and a collector electrode 69 of the bipolar transistor and gates 72 and 82 of the CMOS transistor from the polysilicon film.
In the fourth step, a second insulating film such as a silicon oxide film is formed on the entire upper surface of the semiconductor layer 52 so as to cover the electrodes 67, 68 and 89 and the gates 72 and 82 by a CVD process. Then, a predetermined portion of the second polysilicon film is removed by an etch-back process to form gate side wall insulating films 74 and 84 on side walls of the gates 72 and 82, respectively, and also form a first interelectrode insulating film 70A between the base electrode 67 and the emitter electrode 68 and a second interelectrode insulating film 70B between the emitter electrode 68 and the collector electrode 69, from the second insulating film. Thus, the interelectrode insulating films 70A and 70B of the bipolar transistor and the gate side wall insulating films 74 and 84 of the CMOS transistor are commonly formed from the second insulating film.
There have not been described the step of forming a p-type base region 63, n.sup.+ emitter region 64, p.sup.+ graft base region 65 and n.sup.+ collector drawn region 66 of the NPN bipolar transistor 61, the step of forming a p-type well region 96 of the n-type MOS transistor 71, and the step of forming source and drain regions 73 and 83 of the n-type and p-type MOS transistors 71 and 81.
However, in the bipolar transistor of the Bi-CMOS device shown in FIG. 4, the emitter electrode and the gates are formed from the same polysilicon film. Accordingly, a thickness of the emitter electrode is substantially the same as that of each gate. As a result, accumulation of holes in the emitter is increased to cause an elongation of a travel time in the emitter and therefore elongate a delay time.
Further, in the above manufacturing method, the first insulating film in the CMOS transistor forming region must be covered with a resist in removing a portion of the first insulating film in the bipolar transistor forming region. Accordingly, an impurity in the resist is diffused into the first insulating film contacting the resist, causing a deterioration in quality of the gate insulating film.
Further, the interelectrode insulating film between the emitter electrode and the collector electrode of the bipolar transistor and the gate side wall insulating film of the CMOS transistor are commonly formed from the second insulating film. Accordingly, a thickness of the interelectrode insulating film is decided by a thickness of the gate side wall insulating film, so that a distance between the emitter electrode and the collector electrode cannot be enlarged. As a result, it is difficult to ensure sufficient voltage resistance between the collector and the base of the bipolar transistor. Further, voltage resistance between the emitter and the collector is also reduced.
Additionally, in the case of forming the element isolating region by deeply forming an element isolating diffusion layer, the diffusion layer is diffused laterally to result in an increase in forming area of the element isolating region. Accordingly, high integration is hindered to lower a degree of integration, and a collector--substrate parasitic capacitance is increased to lower an element performance.
Further, an element isolating method using a trench element isolating region requires a step of forming a trench, a step of burying an insulator in the trench, and a subsequent flattening step. Thus, the number of steps is largely increased to result in an increase in manufacturing cost.